A storage system is configured on a plurality of separate substrates each having a buffer memory or a cache memory mounted thereon. Data are transferred between these memories by a DMA controller. Thus, a microprocessor has transmitted a transfer request to the DMA controller for controlling the respective transfers for each data transfer between the memories. This has increased a load on the microprocessor.
When a data transfer in response to a transfer request from the microprocessor is completed, the DMA controller transmits a completion notification to the microprocessor as a requestor. Every time receiving the completion notification, the microprocessor switches a process for processing the completion notification. Thus, the load on the microprocessor has been increased due to this switching overhead.
As such a DMA transfer technology, for example JP 2002-41445 A discloses a DMA controller in which a data transfer controller includes a start command receiving unit and a data transfer request receiving unit for holding the type of a transfer included in a data transfer request for each priority, and the data transfer controller only receives reservation of a request by the data transfer request receiving unit and does not perform a data transfer process. Further, the DMA controller directly holds the types of transfer partners in reservation registers provided for respective priorities and executes a control to transfer data in order from the reservation register having the highest priority until there is no more registered reservation.